Fully depleted lateral transistor

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United States of America Patent

PATENT NO 5583365
SERIAL NO

08200396

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Abstract

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The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.

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Patent Owner(s)

Patent OwnerAddress
SGS-THOMSON MICROELECTRONICS S R LITALY AGRA BRIANZA AGRATE BRIANZA VARESE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ravanelli, Enrico M A Monza, IT 11 74
Villa, Flavio Milan, IT 53 725

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