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United States of America Patent

PATENT NO 5583366
SERIAL NO

08378906

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In the formation and structure of a thin film transistor (TFT), an insulator is formed to cover the surface of the transistor gate electrode, which electrode is separated from an underlying semiconductor layer, having defined source, drain and channel regions, by a gate insulating layer. The overlying gate insulator is formed by anodic oxidation of the gate electrode metal. The formation of the gate insulator thickness and its lateral offset, .DELTA.L, which is defined as the lateral spatial separation between the gate electrode and the source or drain region, can be accurately controlled by the gate electrode anodic oxidation process to provide a reliably and reproducible low OFF current, I.sub.OFF, resulting in a TFT that provides for a large I.sub.ON /I.sub.OFF ratio useful in large area applications wherein electrical charge is required, such as, liquid crystal displays and memory integrated circuits. Preferably, the metal gate electrode is subjected to anodic oxidation at a voltage within the range of between approximately 150 V to 250 V achieving a lateral offset, .DELTA.L, in the range of approximately 100 nm to 200 nm.

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Patent Owner(s)

Patent OwnerAddress
SEIKO EPSON CORPORATIONTOKYO 160-8801

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nakazawa, Takashi Suwa, JP 82 1049

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