Sequencer for a time multiplexed programmable logic device
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United States of America Patent
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Dec 10, 1996
Grant Date -
N/A
app pub date -
Aug 18, 1995
filing date -
Aug 18, 1995
priority date (Note) -
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Abstract
A programmable logic device (PLD) includes at least one configurable element, a plurality of programmable logic elements for configuring the configurable element(s), and a sequencer coupled to the plurality of programmable logic elements. Each programmable logic element typically includes a plurality of memory cells, wherein the sequencer accesses one of the plurality of memory cells during one step in a sequence of steps, each step initiated by one or more trigger signals. If the sequencer receives a plurality of trigger signals simultaneously, then the sequencer prioritizes these signals. Generally, each step provides one configuration of the PLD. In one embodiment, the sequence of steps includes less than all configurations of the PLD. In another embodiment, one trigger signal initiates a plurality of sequences of configurations.
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