Importance

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Abstract

Disclosed is a semiconductor integrated circuit which have a pair of transistors Q11, Q12 with a first polarity being differentially inputted with first logical values A(+) and A(-), a first constant current source I11 for driving the pair of transistors with the first polarity, two pairs of transistors Q13, Q14 and Q15, Q16 with a second polarity, each of the two pairs of transistors being differentially inputted with second logical values B(+) and B(-) and being connected to a drain of each of the pair of transistors with the first polarity, a second and third constant current sources I12, I13 for driving the two pairs of transistors, respectively, and load resistors R11, R12 which are connected to the two pairs of transistors, respectively. The two pairs of transistors Q13-Q16 have one transistor Q13 being connected to one of the load resistors and the other three transistors Q14-Q16 being connected to the other of the load resistors, and an AND output is obtained from a node of one transistor Q13 and the load resistor R11 and an NAND output is obtained from a node of the other three transistors Q14-Q16 and the load resistor R12.

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First Claim