Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
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United States of America Patent
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Dec 10, 1996
Grant Date -
N/A
app pub date -
Dec 9, 1994
filing date -
Dec 9, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention provides balanced cache performance in a data processing system. The data processing system includes a first processor, a second processor, a first cache memory, a second memory and a control circuit. The first processor is connected to the first cache memory, which serves as a first level cache for the first processor. The second processor and the first cache memory are connected to the second cache memory, which serves as a second level cache for the first processor and as a first level cache for the second processor. Replacement of a set in the second cache memory results in the set being invalidated in the first cache memory. The control circuit is connected to the second level cache and prevents replacing from a second level cache congruence class all sets that are in the first cache.
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