Cache control which inhibits snoop cycles if processor accessing memory is the only processor allowed to cache the memory location
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United States of America Patent
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Dec 10, 1996
Issued Date -
N/A
app pub date -
Apr 18, 1995
filing date -
Dec 19, 1991
priority date (Note) -
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Abstract
A multi-processor cache control system wherein cache control information is encoded into the address bits of a memory access request. The encoded cache control information is used to optimize cache control functions. Each memory access request is comprised of at least two elements. First, an address field is provided to define the location of the desired data item. Secondly, cache control information is provided in a cache control field within each memory access request. The cache control field comprises a plurality of bits that define a relationship between the address field and a plurality of local caches associated with processors in a multi-processor system. This relationship determines which of a plurality of local caches may cache the data item referenced by the address within the address field.
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