Semiconductor wafer probing method including arranging index regions that include all chips and minimize the occurrence of non-contact between a chip and a probe needle during chip verification
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United States of America Patent
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Dec 17, 1996
Grant Date -
N/A
app pub date -
Dec 22, 1994
filing date -
Dec 27, 1993
priority date (Note) -
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Abstract
A semiconductor wafer probing method for reducing the number of times of an 'indexing' or wafer transfer operation and improving verification efficiency. In the semiconductor wafer probing method, a probe card has a first plurality of upright probe needles (e.g. sixteen) corresponding to chips (e.g. eight) arranged in a vertical or 'row' direction and chips (e.g. 2) arranged in a horizontal or 'column' direction. A first plurality of chips that can be verified by such a probe card is defined as an index region. A (second) plurality of index regions are arranged so as to minimize the number of occurrences where the probe needles will not have a chip to contact as the wafer and needles are moved relative to each other. Such (second) plurality of index regions is defined as a contact region 23.
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