Structure and method for embedding two small multipliers in a larger multiplier
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United States of America Patent
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Dec 17, 1996
Grant Date -
N/A
app pub date -
Aug 3, 1994
filing date -
Aug 3, 1994
priority date (Note) -
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Abstract
A multiplier circuit which performs selectable multiplication operations on a first word having an upper byte and a lower byte and a second word having an upper byte and a lower byte. A first multiplier circuit generates a first product representative of the product of the upper bytes of the first and second words and the product of the lower bytes of the first and second words. A second multiplier circuit generates a second product representative of the product of the upper byte of the first word and the lower byte of the second word plus the product of the lower byte of the first word and the upper byte of the second word. The second multiplier circuit can be selectively disabled. When the second multiplier circuit is enabled, the multiplier circuit multiplies the first and second words. When the second multiplier circuit is disabled, the multiplier circuit multiplies the upper bytes of the first and second words and the lower bytes of the first and second words.
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