Semiconductor device having a multi-layer channel structure
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United States of America Patent
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Dec 17, 1996
Grant Date -
N/A
app pub date -
Dec 22, 1994
filing date -
Dec 27, 1993
priority date (Note) -
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Abstract
A non-volatile semiconductor memory cell has a channel layer with a two-layered structure including a surface channel layer and a buried channel layer. The operation of reading out '1' level data or '0' level data from the memory cell is effected by using only the buried channel layer and based on whether the conductivity type of the buried layer is inverted or not. The operation of writing '0' level data is effected by using both of the surface channel layer and the buried channel layer, simultaneously inverting the conductivity types of the surface channel layer and the buried channel layer, and passing a current into the inverted layer to generate hot electrons.
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