Importance

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Abstract

A processor within a parallel processing computer having a plurality of processors, where each processor is directly connected to a local storage memory. Each processor contains a principal processing element (PPE), a memory controller, and a multiplexor. The PPE executes a series of program instructions including local storage memory access instructions that cause the PPE to produce a local storage memory access request for accessing information within the local storage memory. The memory controller is connected to the PPE and a plurality of information resources of the parallel processing computer. This controller selectively routes local storage memory access requests from the information resources to an output port of the memory controller and generates an enable flag that is set to a first state when a selected one of the plurality of information resources can access the local storage memory and is set to a second state when the PPE is accessing the local storage such that access by the information resources is deferred until access by the PPE is complete. The multiplexor is connected to the PPE, the memory controller and the local storage memory. The multiplexor, operating in response to the enable flag, multiplexes the PPE access request with the selected information resource access requests such that access by the PPE to the local storage memory occurs substantially without time-delay interruption of the execution of program instructions by the PPE.

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First Claim