Method for estimating routability and congestion in a cell placement for integrated circuit chip

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United States of America Patent

PATENT NO 5587923
SERIAL NO

08301687

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A cell placement for a microelectronic integrated circuit includes a plurality of cells interconnected by nets of wiring. A method for estimating routing density in the placement includes superimposing a pattern of contiguous tiles over the placement, with each of the tiles having edges. Bounding boxes are constructed around the nets, and net probable densities are calculated within each bounding box for the wiring required by each net for each edge respectively. The net probable densities are summed to produce total probable densities of wiring required by all of the nets for each edge respectively. The net probable density for each edge is calculated as being equal to a wiring capacity of the edge divided by the sum of the wiring capacity of the edge and all other unobscured edges within the bounding box that are collinear with the edge respectively. A congestion map can be constructed from the total probable densities and the capacities of the edges, and/or these calculations can be used to predict the routability or unroutability of the placement. Provisions are made for edges that are obscured by large megacells or other obstacles, including providing routing detours around the obstacles.

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Patent Owner(s)

  • BELL SEMICONDUCTOR, LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wang, Deborah C San Jose, CA 1 95

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