CMOS EEPROM cell with tunneling window in the read path
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United States of America Patent
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Dec 24, 1996
Grant Date -
N/A
app pub date -
Nov 6, 1995
filing date -
Nov 6, 1995
priority date (Note) -
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Abstract
A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.
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