Semiconductor memory device including a boost potential generation circuit

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United States of America Patent

PATENT NO 5587958
SERIAL NO

08363825

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Abstract

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A semiconductor integrated circuit device includes a boost potential generation circuit, word line drive system circuit, refresh cycle select circuit, word line system boost potential generation circuit and boost potential generation system control circuit. The boost potential generation circuit steadily generates a higher boost potential than an externally applied voltage. The word line drive system circuit delivers the boost potential, as a power supply, from the boost potential generation circuit so as to drive the corresponding word line. The word line system boost potential control circuit sets at a substantially constant level a boost potential output from the boost potential generation circuit. The boost potential generation system control circuit receives a designation signal from the refresh cycle select circuit so as to designate a refresh cycle and supplies a control signal, which is generated based on the designation signal, to the boost potential generation circuit, whereby, when more word lines are driven at a time by the word line system drive circuit, a current supply capability of the boost potential generation circuit is increased and, when less word lines are driven at a time, the current supply capability of the boost potential generation circuit is decreased.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBATOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kaneko, Tetsuya Kawasaki, JP 236 6798
Ohsawa, Takashi Yokohama, JP 187 5504

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