Importance

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Abstract

A digital information receiver having a single oscillator providing a clock signal to the receiver circuitry. The receiver contains, in addition to the oscillator, an input signal processor, a symbol timing loop, a demodulator, a transport decoder, a transport timing loop, one or more applications decoders and a presentation device. The input signal processor digitizes an input signal and resamples the input signal using an interpolator such that the input signal is optimally sampled. The resampling is controlled by a symbol timing loop. In a first embodiment, the transport timing loop controls the frequency of the oscillator using transmitter timing information contained in the received signal. In a second embodiment, the oscillator is a free running oscillator and the transport timing loop controls a numerically controlled counter that, in turn, controls presentation timing of the information carried by the information in the input signal. After the input signal is decoded, an output interpolator generates continuous signals from somewhat bursty signals for utilization by the presentation device.

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First Claim