Method for a hybrid leadframe-over-chip semiconductor package
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United States of America Patent
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Dec 31, 1996
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Sep 13, 1994
priority date (Note) -
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Abstract
A hybrid leadframe-over-chip (LOC) semiconductor package is generally comprised of bonding finger elements located over a surface of a semiconductor component and electrically coupled, by means of conducting wires, to the bonding pads located on the surface. In addition, at least one bonding finger is located outside the boundary of the surface of the semiconductor component. Each bonding finger located outside the boundary is coupled, by a conducting wire, to a bonding pad positioned within the boundary of the semiconductor component. In this manner, for a given semiconductor component size and for given routing and lead dimension constraints, a larger number of conducting paths can be provided between the leadframe and the semiconductor component.
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