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Abstract

To recognize a specific pattern of bits anywhere within a high-speed bit stream of data, the serially-received bytes of the bit stream are first converted to parallel or simultaneously-presented, eight-bit bytes. Received bytes are used as the addresses of two SRAMs. A byte of the desired pattern is recognized by having that byte address a memory location of one of the SRAMs in which a binary '1' has been stored at the bit location within that memory location that corresponds to the received byte's position within the expected bit pattern. The other seven bit locations within that memory byte have binary '0s' stored in them. The outputs from the two SRAMs are gated to look for a sequence of two successive bytes of the expected pattern. A binary '1,' signifying recognition of receipt of two successive bytes, is clocked into one of a plurality of shift registers. The length of each shift register represents the opposite of the position, within the expected sequence pattern, of the two successive bytes. The outputs of the shift registers are all connected to inputs of an AND-gate, the output of which indicates a match with the respected sequence pattern. As each successive pair of received bytes is clocked into the address registers of the SRAMs, the shift registers are clocked to advance their stored bits by one stage.

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