Protocol parallel processing apparatus having a plurality of CPUs allocated to process hierarchical protocols

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United States of America Patent

PATENT NO 5590328
SERIAL NO

08399331

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Abstract

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A protocol processing apparatus is presented having a plurality of CPUs for processing communication protocol data in parallel so as to achieve a high measure of efficiency. The apparatus provides a common memory including a CPU state table that is accessible by the plurality of CPUs. The CPU state table associates an idle flag, a remote node identifier, and a process start time with each of the plurality of CPUs. At least one line interface selects a CPU from the plurality of CPUs according to the contents of the CPU state table, selecting an idle CPU if one is available, selecting a CPU with the oldest process start time if no idle CPU is available, or selecting a busy CPU if the communication data to be processed is related to communication data already running on the busy CPU.

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Patent Owner(s)

  • MITSUBISHI DENKI KABUSHIKI KAISHA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ideguchi, Tetsuo Kanagawa-ken, JP 2 142
Seno, Shoichiro Kanagawa-ken, JP 5 154

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