Vector processor adopting a memory skewing scheme for preventing degradation of access performance
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United States of America Patent
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-
Dec 31, 1996
Grant Date -
N/A
app pub date -
Jul 15, 1994
filing date -
Jul 15, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.
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