Reduction of surface copper thickness on surface mount printed wire boards with copper plated through holes by the chemical planarization method
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United States of America Patent
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Jan 7, 1997
Grant Date -
N/A
app pub date -
Aug 18, 1994
filing date -
Aug 18, 1994
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method of fabricating a printed wiring board (1) and a printed wiring board module (17) by providing a first board (1) having a pair of major opposing surfaces, a via (3) having walls extending between the surfaces and a layer of copper (5) disposed on at least one surface and extending along the walls of the via. The copper disposed in the via is protected against a subsequent etching of the copper on the surface by filling the remaining portion of the via with an epoxy (7) and then reducing the thickness of the layer of copper on the surface. The layer of copper and the epoxy are then planarized. A core layer and a second board are then provided and the first and second boards are secured to opposing sides of the core layer. A second via having walls and extending through the first and second boards and the core layer is then formed and a layer of copper is disposed on the walls of the second via and the surface. The electrically conductive material on the surface is then patterned and etched to form an electrically conductive pattern.
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