Sealed cavity arrangement method
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United States of America Patent
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Jan 7, 1997
Issued Date -
N/A
app pub date -
Jan 30, 1996
filing date -
Apr 12, 1995
priority date (Note) -
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Abstract
This invention relates to a method for making sealed cavities on silicon wafer surfaces by anodic bonding and with electrically insulated conductors through the sealing areas to connect functional devices inside the cavities to electrical terminals outside said cavities. Said conductors are provided by the use of doped buried crossings in a single crystal silicon substrate, thereby also allowing different kinds of integrated silicon devices, e.g. sensors to be made. Further, the invention relates to a device made by the novel method.
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