Configuration logic to eliminate signal contention during reconfiguration
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United States of America Patent
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Jan 7, 1997
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app pub date -
Jan 20, 1995
filing date -
Jan 20, 1995
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Abstract
A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.
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