High resolution image processor with multiple bus architecture
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United States of America Patent
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Jan 7, 1997
Grant Date -
N/A
app pub date -
Nov 4, 1994
filing date -
Nov 4, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multiple video data bus architecture permits high speed data transfer among the various circuit elements of a fluoroscopic imaging processor. This permits simultaneous acquisition, storage, display, and image enhancement of high resolution, i.e., 2K.times.2K images. A memory interface circuit compresses the video data for storage in bulk memory. The processor supports several high-resolution monitors which can respectively display radiographic images from different subjects, so that review and diagnosis can occur remotely.
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