Importance

Loading Importance Indicators...

Abstract

Methods and apparatus are presented for unobtrusively monitoring processor states and characterizing bottlenecks in an arbitrary customer workload. An instruction queue and an instruction control unit within a pipelined central processor unit (CPU) provide for grouping and issuing multiple instructions per clock cycle for overlapped execution. Additionally, instruction and data caches in operation with integer and floating point function units issue a program counter to the instruction cache, which subsequently supplies instructions to integer and floating point instruction queues. Both integer and floating point unit datapaths comprise fetch, decode, execute, and writeback stages. In the preferred embodiment, ten additional datalines transmitting PIPE signals are routed from the integer and floating point function units to contact pins on an external pin gate array supporting the CPU. The ten PIPE signals provide information on activity of key internal states of the pipelined processor within a single clock cycle. The PIPE signals may be monitored by a logic analyzer, thereby forming an external hardware monitor. By tracing the ten PIPE signals, the number of instructions issued in each stall-free cycle and total number of cycles elapsed may be determined, permitting determination of bottlenecks in customer software on the target CPU, as well as yielding information for optimizing the CPU to execute customer software more efficiently. Based on the accumulated and tabulated performance data, a CPU vendor can reconfigure hardware and/or software to more precisely meet customer workload needs based on determination of customer software operating in the customers actual work environment.

Loading the Abstract Image...

First Claim