Arbitration protocol for a bidirectional bus for handling access requests to a logically divided memory in a multiprocessor system
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United States of America Patent
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Jan 14, 1997
Issued Date -
N/A
app pub date -
Jul 27, 1995
filing date -
Jun 24, 1992
priority date (Note) -
Expired
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Abstract
The invention concerns a multiprocessor system comprising processors PU0 to PUn and a common main memory. The memory is logically divided into at least two banks M0 and M1 and is interconnected with the processors by a bus 110. By means of control lines 111 to 118 a bus protocol is established so that one of said memory banks is accessed while another one of said banks is still busy.
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