Semiconductor memory device
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United States of America Patent
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Jan 21, 1997
Grant Date -
N/A
app pub date -
Dec 4, 1995
filing date -
Dec 8, 1994
priority date (Note) -
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Abstract
In a semiconductor memory device, data required for controlling design margins and access time is stored at a selected fuse ROM array and a vendor test is performed. By using the information obtained by the vendor testing, fuse ROM arrays are programed, so that design margins and access time can be easily varied according to semiconductor memory device, thereby enhancing the device performance. Moreover, by additionally adapting a multiplexer, a plurality of fuse ROM arrays can be programmed by using a few pads.
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