Importance

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Abstract

A method of improving efficiency in computer systems through a novel arbitration scheme is disclosed. The arbitration scheme includes a bus arbiter circuit that transparently operates in both central arbitration and distributed arbitration computer systems. The bus arbiter circuit includes an arbitration request sequencer, an arbitration competition protocol sequencer, a multiplexer, a latch, two comparators, and a series of control status registers that together provide increased system efficiency by effectively self-preempting competition priorities on its own board, thus allowing tasks with the highest priorities to compete for mastership of the bus and eliminating priority inversions.

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First Claim