Comparator cell for use in a content addressable memory
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United States of America Patent
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Jan 28, 1997
Issued Date -
N/A
app pub date -
Feb 8, 1995
filing date -
Feb 23, 1993
priority date (Note) -
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status (Latency Note)
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Abstract
A content-addressable memory wherein match transistors are prevented from discharging a match line by either placing transistors in series with the match transistors and only turning them on during a match sensing period, or a match sense line which is driven near the precharge voltage of the match line until the match sensing period. The match sensing line also provides charging current to recharge the match line. For some applications, a differential match line amplifier is used to detect matches and mismatches. The match sense line can be used with a CAM having a four-transistor comparator. The invention is also applicable to match lines in programmable-array logic (PAL) cells, and for either NMOS or PMOS circuits.
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