Importance

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Abstract

In a multi-processing system (10), a cache controller is implemented to efficiently process collisions which occur when a predetermined address location in a data memory (26) is simultaneously accessed by two processors (20, 21). The cache controller is formed by both a cache control logic circuit (34) and a tag unit (36). In the tag unit (36), a snoop tag cache (40) and a data tag cache (42) respectively indicate whether a snooped value or an accessed data value is stored in data memory (26). A status bit array (41) provides status information for both tag caches (40, 42). By configuring the array (41) to store status information for both snoop and data tag caches (40, 42), status information is 'forwarded' between tag caches (40, 42) when a collision occurs. Additionally, the cache controller modifies the timing of each of the accesses such that the status information may be 'forwarded' more easily. The timing modification is also referred to as 'resource pipelining.'

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First Claim