Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles
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United States of America Patent
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Jan 28, 1997
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app pub date -
Feb 15, 1996
filing date -
Jul 16, 1993
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Abstract
By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition cycles to accomplish cache address invalidations both during a cache hit or a cache miss cycle, the present architecture and methodology permits a faster cycle of cache address invalidations when required and also permits a higher frequency of processor access to cache without the processor being completely locked out from cache memory access during heavy traffic and high level of cache invalidation conditions.
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