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Abstract

A modulation apparatus for converting digital data having the basic data length equal to m bits into a variable length code (d, k; m, n; r) having the basic codeword length of n bits is disclosed. The apparatus includes an encoder 12 for determining the constraint length i of data supplied from a shift register 11, based upon m bits as a unit, a selector 13, plural conversion tables 14.sub.1 and an unfixed bit processing circuit 16.sub.1. The selector 13 selects one of the conversion tables 14.sub.1 based upon the constraint length i and transmits m.times.i bit data to the selected conversion table 14.sub.1, which then converts the m.times.i bit data into n.times.i bit codewords. The unfixed bit processing circuit 16.sub.1 sets a bit at a preset position of a codeword among the codewords which gives an infinite value of the maximum run, or a bit at a preset position of a codeword among the codewords which has the maximum number of consecutive '0's from the least significant bit towards upper order side bits, as being an unfixed bit, and sets the unfixed bit to '1' if d or more '0's are consecutive to the unfixed bit. With the present modulation apparatus, the minimum length between transitions T.sub.min may be enlarged as compared to that in EFM for increasing the recording density, while the maximum length of transitions T.sub.max may also be increased as compared to that for VFM.

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