Register protection structure for FPGA
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United States of America Patent
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-
Feb 4, 1997
Grant Date -
N/A
app pub date -
Jun 6, 1995
filing date -
May 2, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
In an FPGA having registers which are part of a user's logic functions and a configuration memory which is read and written through an addressing structure, a register protect circuit controllably protects the contects of these user logic registers from being modified by signals from the user's logic, allows these registers to be written by a microprocessor through the configuration memory addressing structure, and allows both the user's registers and lines which provide combinational signals to be read by a microprocessor through the configuration memory addressing structure.
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