Memory cell and wordline driver for embedded DRAM in ASIC process
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United States of America Patent
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-
Feb 4, 1997
Grant Date -
N/A
app pub date -
Dec 14, 1994
filing date -
Dec 14, 1994
priority date (Note) -
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Importance
Abstract
A DRAM charge storage structure including a p-channel access FET in an n.sup.- doped well of a p.sup.- doped substrate, a p.sup.- channel charge storage capacitor, conductive apparatus connecting a gate of the charge storage capacitor to a drain of the FET, and apparatus for applying a boosted word line voltage to a gate of the FET.
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