Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same
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United States of America Patent
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Feb 4, 1997
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N/A
app pub date -
Mar 7, 1996
filing date -
Aug 31, 1995
priority date (Note) -
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Abstract
A method of operating a memory device including a plurality of data/address input/output terminals, an array of memory cells and circuitry for accessing selected ones of the memory cells in response to received address bits. At least one row address bit and at least one column address bit are substantially simultaneously input during an address cycle, at least one of the address bits being input through a selected one of the multiplexed terminals. The memory cells addressed by the row and column bits are then accessed through selected ones of the multiplexed terminals during a data access cycle.
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