Scaleable very long instruction word processor with parallelism matching
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United States of America Patent
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Feb 4, 1997
Grant Date -
N/A
app pub date -
Dec 9, 1994
filing date -
Dec 9, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system is provided to increase the efficiency of a VLIW, Very Long Insttion Word, processor which matches its level of parallelism, LOP, to the LOP of the executable code before executing the code's fixed-length VLIW instructions, so that object-level code compatibility is kept for different processor implementations of the same VLIW architecture required for different applications. Matching is accomplished either by reducing the LOP of the processor via inactivating the processor's functional units, or by effectively reducing the LOP of the executable code via the processor executing the sequential portions of each VLIW instruction in the code, with the length of the portions equal to or less than the number of operations that the processor can handle as a VLIW instruction.
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