Multitask processor architecture having a plurality of instruction pointers
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United States of America Patent
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Feb 4, 1997
Grant Date -
N/A
app pub date -
May 24, 1994
filing date -
May 27, 1993
priority date (Note) -
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Abstract
A processor architecture for executing a current task among a plurality of possible tasks. The architecture includes: a plurality of instruction pointers respectively associated with the tasks and each storing the address of the current instruction to be executed of the associated task, only one of these pointers being enabled at a time to supply an address to the memory; a priority level decoder including circuitry for assigning a predetermined priority level to each request signal and for enabling the instruction pointer associated with the active request signal having the highest priority level; and a mechanism for incrementing the content of the enabled instruction pointer and for reinitializing it at the start address of the associated program when its content reaches the end address of the associated program.
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