Importance

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Abstract

A system and method for controlling a peripheral bus clock signal through a slave device are provided that accommodate a power conservation scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. Prior to stopping the peripheral bus clock signal, an indicator signal is generated at a clock request line by a clock control circuit. If the slave device continues to require the peripheral bus clock signal, the slave device responsively generates a clock request signal. The clock control circuit receives the clock request signal and accordingly prevents the peripheral bus clock signal from stopping. The system may further allow an alternate bus master to assert the clock request signal to re-start the peripheral bus clock signal after it has stopped. The alternate bus master can thereby generate a synchronous bus request signal to attain mastership of the peripheral bus. As a result of the system, a slave device can prevent the stopping of the peripheral bus clock signal at the completion of a peripheral bus cycle if the clock signal continues to be required. The system further accommodates a power management scheme in which the peripheral bus clock signal can be stopped and that allows an alternate bus master to re-start the peripheral bus clock signal.

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First Claim