Importance

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Abstract

Digital signal processing often requires the fast summing of a chain of products. Known signal processors often use two separate dam buses via which the values to be multiplied are supplied in parallel, it being assumed that these values originate from different sources, for example from different memories. Because a product of two binary numbers has double the number of positions, therefore, an adder having double the word width is also used. In order to reduce this substantial expenditure at the expense of only a slight reduction in speed, an adder is provided having only the single word width and to process the most-significant and least-significant bits of the product during two successive clock periods. The values to be multiplied can then be supplied successively.

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First Claim