Importance

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Abstract

An associative memory device of the present invention capable of operation at high speed and a reduced power consumption comprises: a memory array; precharge circuits each provided for each pair of a data line and an inverted data line in the memory array to precharge the data lines and the inverted data lines to a precharge potential in a standby mode before at least a data retrieval operation; and data line drivers each provided for the each pair of the data line and the inverted data line to drive the data lines and the inverted data lines to one of a HIGH logic level and a LOW logic level at least in the data retrieval mode, wherein the precharge potential of the data lines and the inverted data lines is lower than a supply potential and higher than a ground potential, preferably, a middle potential between the supply potential and the ground potential.

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First Claim