Importance

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Abstract

When a processor generates an access request to a plurality of continuous addresses to an RAM through a memory control apparatus, in order to enable a high speed process, a register which holds an address for accessing a memory cell and a register which holds an address for accessing a data buffer are separately provided in an RAM having memory cells and a plurality of row correspondence data buffers of the memory cells. A signal line to instruct the presence or absence of the use of the data buffer is provided between the processor and the memory control apparatus. The memory cell and the data buffer are accessed in parallel, thereby realizing a high processing speed. The processor designates so as to preferentially use the data buffer for an RAM access having an address continuity, thereby enabling the data to be accessed at a high speed.

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First Claim