Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller
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United States of America Patent
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Feb 11, 1997
Issued Date -
N/A
app pub date -
Aug 22, 1995
filing date -
Mar 12, 1991
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Abstract
An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.
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