Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit
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United States of America Patent
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Feb 11, 1997
Issued Date -
N/A
app pub date -
Apr 30, 1990
filing date -
Dec 28, 1970
priority date (Note) -
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Abstract
Memory technologies for storing filter samples include RAMs and CCDs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.
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