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Abstract

A configurable hardware system for implementing an algorithmic language program, including at least two programmable logic devices (PLD), a private hardware resource connectible to one PLD, and a programmable connection between PLDs, all of which may be configured as a module or distributed processing units (DPU). The private hardware resource may include a serial processing device such as a DSP, a PLD, a memory device, or a CPU. An extensible processing unit (EPU) can be built out of multiple DPUs, each connected to other modules by one or more of several buses. An N-bus (neighbor bus) connects a module to its nearest neighbor, an M-bus (module bus) connects a group of modules, and an H-bus (host bus) connects a module to a host CPU. The invention also includes a method of translating source code in an algorithmic language into a configuration file for implementation on one or more DPUs. The method includes four sequential phases of translation, a tokenizing phase, a logical mapping phase, a logic optimization phase, and a device specific mapping phase.

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First Claim