Method for forming a multilayer integrated circuit

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United States of America Patent

PATENT NO 5604137
SERIAL NO

08460632

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A multilayer semiconductor integrated circuit which does not suffer from latchup. The circuit comprises a semiconductor substrate, a first MOS transistor formed on the substrate, an interlayer insulator deposited on the first transistor, and a second MOS transistor formed on the interlayer insulator. The two transistors have different conductivity types. The gate electrode of the second transistor consists mainly of metal or metal silicide, e.g. aluminum. The upper and side surfaces of the gate electrode is coated with a material comprising an oxide of the metal or metal silicide.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
Semiconductor Energy Laboratory Co., Ltd.KANAGAWA-KEN10848

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mase, Akira Aichi, JP 150 6482
Takemura, Yasuhiko Kanagawa, JP 561 28394
Uochi, Hideki Kanagawa, JP 141 7365
Yamazaki, Shunpei Tokyo, JP 5614 141624

Cited Art Landscape

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