Method for forming a multilayer integrated circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5604137
SERIAL NO

08460632

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A multilayer semiconductor integrated circuit which does not suffer from latchup. The circuit comprises a semiconductor substrate, a first MOS transistor formed on the substrate, an interlayer insulator deposited on the first transistor, and a second MOS transistor formed on the interlayer insulator. The two transistors have different conductivity types. The gate electrode of the second transistor consists mainly of metal or metal silicide, e.g. aluminum. The upper and side surfaces of the gate electrode is coated with a material comprising an oxide of the metal or metal silicide.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
SEMICONDUCTOR ENERGY LABORATORY CO LTD398 HASE ATSUGI-SHI KANAGAWA-KEN 243-0036

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mase, Akira Aichi, JP 150 6620
Takemura, Yasuhiko Kanagawa, JP 570 29237
Uochi, Hideki Kanagawa, JP 157 7892
Yamazaki, Shunpei Tokyo, JP 6075 159508

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation