Reduced notching of polycide gates using silicon anti reflection layer
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United States of America Patent
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Feb 18, 1997
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N/A
app pub date -
May 25, 1995
filing date -
May 25, 1995
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Abstract
A method for fabricating MOSFET devices, with narrow gate structures, and narrow spaces between gate structures, has been developed. The addition of a rough surfaced silicon layer, as part of the gate structure, minimizes the amount of reflective and scattered light, resulting during the gate photolithographic processing. The reduction in reflective and scattered greatly enhances the ability to achieve sub-micron lines and spaces. The rough surfaced silicon can remain as a part of the gate structure, and is obtained by chemical vapor deposition of either an amorphous silicon, or a hemi-spherical grained silicon film.
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