Virtual interface representation of hierarchical symbolic layouts
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United States of America Patent
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Feb 18, 1997
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N/A
app pub date -
Aug 15, 1994
filing date -
Aug 15, 1994
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Abstract
A method and system provide for the symbolic design of a symbolic layout of an integrated circuit using only the topological features of the cells of the layout, absent geometrical information. Virtual leaf cells define circuit elements, and virtual hierarchical cells combine virtual leaf cells and other virtual hierarchical cells into hierarchical arrangements using interface graphs. Virtual interfaces describe the connectivity and orientation relations between virtual cells. The interfaces inherit the definitional requirements of interfaces at lower levels. The symbolic layout is produced from a hierarchy of virtual cells using hierarchical compaction and routing technology.
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