DRAM having multiple column address strobe operation
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United States of America Patent
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Feb 18, 1997
Grant Date -
N/A
app pub date -
Nov 30, 1995
filing date -
Nov 30, 1995
priority date (Note) -
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Abstract
A dynamic memory device is described which has multiple column address signal inputs. Data can be stored in the memory and selectively read therefrom. The column address signals are used to control the data communication. During a read operation, any one of the multiple column address signal inputs can be used to output data on all external communication lines. During a write operation, each column address signal input writes data from a portion of the external communication lines to the memory device.
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