Data processing system having load dependent bus timing
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United States of America Patent
Stats
-
Feb 18, 1997
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Aug 3, 1989
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A data processing system in which timing of data transfer operations are adjusted in response to bus load variation is disclosed herein. The data processing system includes a microprocessor having a sensing circuit, and a driver circuit disposed to impress a signal upon a control line. The control line is also connected to the sensing circuit, as well as to one or more devices external to the microprocessor. The sensing circuit is configured to monitor a response time required for the signal impressed upon the control line to reach a predetermined electrical level, wherein the response time is a function of the number of devices coupled to the control line. The microprocessor is disposed to adjust the timing of data transfer between the microprocessor and the one or more devices external to the microprocessor based upon the monitored response time.
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