Process for fabricating a graded-channel MOS device

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United States of America Patent

PATENT NO 5605855
SERIAL NO

08395339

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Abstract

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A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).

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Patent Owner(s)

Patent OwnerAddress
MOTOROLA INC1303 EAST ALGONQUIN ROAD SCHAUMBURG IL 60196 U S A

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Ko-Min Austin, TX 44 1537
Luo, Shiang-Chyong Austin, TX 1 40
Orlowski, Marius Austin, TX 26 525
Sun, Shih-Wei Austin, TX 79 2357
Swift, Craig Austin, TX 4 118

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