Address generator with controllable modulo power of two addressing capability
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United States of America Patent
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Feb 25, 1997
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Nov 17, 1989
priority date (Note) -
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Abstract
A data processing address generator includes a plurality of address registers, a plurality of index address registers, a modulo register storing a plurality of carry break indicators and an arithmetic unit. The arithmetic unit adds or subtracts a selected address register and a selected index register. The arithmetic unit generates a normal carry between a particular bit and the next more significant bit if a corresponding carry break indicator stored in said modulo register has a first digital state. The arithmetic unit breaks any carry between the particular bit and the next more significant bit if the corresponding carry break indicator has a second digital state. The carry break may be dependent upon a modulo qualifier bit being in an enabling state. The modulo qualifier bit may be stored in one of a plurality of qualifier registers corresponding to the address registers.
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