EEPROM array with flash-like core
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United States of America Patent
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Feb 25, 1997
Grant Date -
N/A
app pub date -
Mar 17, 1995
filing date -
Mar 17, 1995
priority date (Note) -
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Abstract
A sector programmable EEPROM memory capable of emulating the byte programmable functionality of full-featured byte programmable EEPROMs. The EEPROM memory incorporates an on-chip write cache used as a buffer between byte level data entered by the user system and word level data written to the main memory core. The EEPROM main memory core is divided into memory pages with each memory page further divided into sub-page sectors, and each sub-page sector holding a multitude of multi-byte data words. The sub-page sectors within a memory page can be individually or collectively subjected to a program and erase cycle. The EEPROM memory incorporates an ECC unit used to recover and refresh lost data in the memory core. The EEPROM memory is also capable of interruptible load cycles.
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